This invention relates to a method for manufacturing a semiconductor memory device having a memory cell structure consisting of one transistor and one capacitor.
A MOS dynamic RAM (hereafter "dRAM") having memory cells formed of one MOS transistor and one MOS capacitor is known in the art. In a dRAM cell, data is stored by the presence or absence of electric charge in a capacitor, and data is read by releasing the electric charge stored in a capacitor through the transistor into a bit line.
In recent years, advances in semiconductor production techniques, particularly in the fine processing technique, has encouraged the growth of dRAM capacity. A chief obstacle to increasing dRAM capacity further is how to decrease the surface area of a memory cell while increasing or maintaining the capacitance of cell capacitor. This is important since the size of the potential change which results when reading a capacitor's electric charge must not be too low. The minimum amount of electric charge is fixed according to an allowance for operation and an allowance for noise, such as from alpha rays. Since the amount of stored electric charge depends on the capacitance of the cell capacitor and the applied voltage, and since the applied voltage is determined by the power source voltage, one must adjust the capacitance of the cell capacitor to maintain sufficient charge storage.
In the conventional dRAM described above, it becomes necessary to decrease the thickness of the gate insulation film, increase the dielectric constant, or widen the surface area to increase the cell capacitance. Any decrease in the thickness of the insulation film, however, is limited by considerations of reliability. To increase the dielectric constant, a nitride film (Si.sub.3 N.sub.4) may be used in place of an oxide film (SiO.sub.2), for example, but the use of nitride film lacks sufficient reliability.
Therefore, to acquire the necessary capacitance, the surface area of a capacitor must be made sufficiently large. The need for a large surface area, however, is generally at odds with attempts to reduce memory cell surface area and increase dRAM density and capacity.
To maintain a large dRAM cell capacitance without increasing the surface area occupied by that cell, some have proposed forming grooves in the surface of the semiconductor substrate at the MOS capacitor region in order to use the side walls of the grooves as MOS capacitors. K. Itoh, et al. "An Experimental 1Mb dRAM with On-Chip Voltage Limiter," ISSCC Technical Digest 282-83 (1984) shows one such method. Conventional dRAM fabrication uses only the flat surface of the substrate, but the method in the Itoh et al. article requires extremely fine and deep grooves. The small openings of such fine grooves impose severe restrictions.
Two other approaches to the problem of maintaining capacitance while decreasing size are the Corrugated Capacitor Cell (CCC) and the Folded Capacitor Cell (FCC). The CCC increases capacitance by making a trench in the capacitor regions and using the walls and bottoms of the trench as part of the capacitor. This method is described in greater detail in H. Sunami et al., IEEE Electron Device Letters, Vol. EDL-, pp. 90-91 (1983). One disadvantage of this approach is that the capacitance is limited by the opening of the trench. As the area of the opening decreases, the trench must be deepened to maintain the capacitance. Deepening the trench, however, causes leakage problems from punch-through between neighboring trenches.
The FCC is discussed in detail in M. Wada et al., "A Folded Capacitor Cell (F.C.C.) for Future Megabit DRAMs," IEDM, pp. 244-247 (1984) and Japanese Patent Disclosure No. 58-212161 (Sept. 12, 1983). This cell uses a vertical capacitor made along the isolation region. Two disadvantages of this cell are the difficult PEP (Photo Engraving Process) of the gate electrode and the capacitor plate due to the uneven substrate, and the large capacitance of the gate electrode at the side walls of the Si island which reduces the switching speed of the device.
An object of this invention is a method for manufacturing a semiconductor memory device, as well the device, with reduced memory cell surface area, but which has an ample capacitance for the cells' capacitors and enables future growth of memory capacity.
Another object of the present invention is a superior method for manufacturing a semiconductor device which permits safe PEP of the gate electrode and results in a high speed memory device.
Additional objects and advantages of the present invention will be set forth in part in the following description and in part will be obvious from that description or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by the methods and apparatus particularly pointed out in the appended claims.